In the manufacture of integrated circuits, photolithographic processes are commonly used, in which a wafer is patterned by projecting radiation through a patterned mask to form an image pattern on a photo sensitive material, referred to as a photoresist, or simply resist. The exposed resist material is developed to form openings corresponding to the image pattern, and then the pattern is transferred to the wafer substrate by methods such as etching, as known in the art.
The basic lithography system consists of a light source, a photomask containing the pattern to be transferred to the wafer, a collection of lenses, and a means for aligning existing patterns on the wafer with patterns on the mask. The mask design process as described herein covers the steps from chip design, model-based optical proximity correction (OPC), OPC Verification and mask fabrication. Such mask design processes typically rely on accurate numerical models of the imaging processes, which are herein referred to as lithographic models, which provide predictions of the images produced by various lithographic processes, such as optical imaging and resist processes, as well as images resulting from other processes such as resist, etch and chemical-mechanical polish (CMP) process images.
A lithography stepper is limited by parameters described in Rayleigh's equation:
                    R        =                              k            1                    ⁢                      λ            NA                                              Eq        .                                  ⁢        1            where λ is the wavelength of the light source used in the projection system and NA is the numerical aperture of the projection optics used. The highest resolution in optical lithography is currently achieved with deep ultra violet (DUV) steppers operating at 193 nm wavelength. Steppers operating at wavelengths of 248 and 365 nm are also in widespread use. k1 is a factor describing how well a combined lithography system can utilize the theoretical resolution limit in practice and can range from 0.8 down to <0.5 for standard exposure systems.
OPC tools attempt to optimize the photomask design to compensate for optical effects on the pattern transfer process that originate from the lithographic process, which includes the steps of resist, exposure and etch. Such optical effects include pitch-dependent linewidth variations, flare, corner rounding and line-end shortening. An OPC tool optimizes a mask design by modifying mask features from the original designed polygons, typically by moving edge fragments, to ensure that layout features print according to specifications. The model-based OPC (MBOPC) flow typically consists of contour generation simulated by a lithographic process model, followed by optimization to reduce geometric error between the resist contour and a target feature. However, under low-k1 lithography processes typically in use, the printing of perfect polygons is practically impossible to achieve. This in turn leads to errors in electrical properties of the printed patterns relative to the desired design.
To address the errors in electrical properties, electrically-driven optical proximity correction (ED-OPC) has been proposed. ED-OPC uses electrical matching directly as an objective of OPC. An ED-OPC tool combines lithography simulation with accurate electrical modeling of resist contours to predict the on/off current through a transistor gate. The computation of mask edge movements is cast as a linear program based on both optical and electrical sensitivities. The objective is to minimize the error in saturation current between printed and target shapes. This approach has resulted in improved timing accuracy as compared to conventional geometrically-based OPC optimization. Banerjee et al. (“Compensating Non-Optical Effects using Electrically-Driven Optical Proximity Correction,” Proc. of SPIE, Vol. 6925, pp. 69251W-1-69251W-9 (2008)) disclosed the use of ED-OPC to compensate for other sources of process variation, such as well implant proximity effect, rapid thermal annealing (RTA) variations and stress variations. However, ED-OPC is more time consuming and costly than conventional OPC.
Another approach to address electrical errors has been disclosed by Culp et al. (US 2007/0106968). Culp et al. disclose identifying timing sensitive devices that are within a critical timing path of an integrated circuit, generating an additional mask by a selective trim to shorten the gate lengths of the timing sensitive devices, without shortening gate lengths of devices that are not within the critical timing path, and generating new timing rules for the trimmed devices and comparing the new timing rules to product requirements, and repeating the steps for the identified timing sensitive devices until product requirements are met. However, the method disclosed by Culp et al. is implemented during the design phase and is not easily modified to account for process variations which may not be known during the design phase.
In view of the above, there is a need for a method to provide a mask optimization methodology that can more rapidly and effectively account for process variability while meeting electrical product requirements.